This invention relates to a method and structure for reducing short-gate effects in field effect transistors.
FIG. 1 illustrates in cross section a conventional Schottky FET constructed from gallium arsenide. Referring to FIG. 1, the Schottky FET includes an ohmic metal source contact 1, a metal Schottky gate 2, and an ohmic metal drain contact 3 formed on an N type gallium arsenide channel layer 4. Channel layer 4 is formed on a semi-insulating gallium arsenide substrate 5. Portions of channel layer 4 underneath ohmic source contact 1, gate 2, and ohmic drain contact 3 serve as the transistor source, channel, and drain, respectively. Conductivity of the Schottky FET channel between the source and drain is modulated by controlling the size of the depletion region between Schottky gate 2 and channel layer 4.
Unfortunately, during operation, the electric field in the Schottky transistor of FIG. 1 tends to route current carriers through paths deep into substrate 5. FIG. 2 illustrates the Schottky transistor of FIG. 1 including field lines 6. The current carriers (electrons) of the Schottky transistor follow the lines of (but flow in a direction opposite to) electric field lines 6 which extend deep into substrate 5 and far from gate 2. Because of this, a significant portion of the current flowing between the source and drain of the Schottky transistor is not strongly influenced by the electrical potential at gate 2. This results in lowet transconductance, especially as the transistor approaches pinch-off. This also results in higher source to drain conductance for the transistor than would be achieved if electron flow were confined to an area close to gate 2. These effects are particularly severe when the gate length L is very short. Thus, the above-described effects are commonly known as short-gate effects.
One method for mitigating short-gate effects is described by Tohru Takada, et al., in "A Two Gb/s Throughput GaAs Digital Time Switch LSI Using LSCFL" published at the IEEE 1985 Microwave and Millimeter Wave Monolithic Circuits Symposium at St. Louis, Mo. on June 3, 1985. Takada forms a P type region underneath an N type transistor channel using ion implantation. Unfortunately, the Takada process has a number of drawbacks. For example, the amount of P type dopant which may be implanted underneath the Takada channel is extremely limited because if too much P type dopant is implanted into the Takada transistor, the N type region under the Takada gate may be excessively counter doped. Further, the P type layer underneath the Takada channel cannot be formed to an extremely shallow depth (e.g., 100 to 1000 .ANG.) with good control. Also because Takada uses ion implantation, impurities are lodged in the transistor channel region, which causes scattering effects and reduces electron velocity, thereby reducing transconductance.